1. Field of the Invention
The present invention relates to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal.
2. Description of the Related Art
In general, a synchronous semiconductor device is operable in sync with an external clock signal outputted from a controller of the semiconductor device. Such an operation is also applied to a synchronous memory device. That is, a synchronous memory device is operable in sync with an external clock signal output from a memory controller. In operation, it is usual that a memory device receiving an external clock signal generates an internal clock signal in addition, which is necessary to conduct internal operations.
FIG. 1A illustrates an external clock signal with a frequency of 100 MHZ outputted from a memory controller and an internal clock signal generated in a memory device. In FIG. 1A, the reference character CLK denotes the external clock signal and CLKB denotes a signal reverse to the CLK in phase. As illustrated in FIG. 1A, the memory device receiving the external clock signal CLK generates the internal clock signal that is used to conduct internal operations.
A general reason for additionally generating an internal clock signal used in a memory device is as follows.
In FIG. 1A, as a cycle period of the external clock signal of 100 MHz is 10 ns, a half of the cycle period is 5 ns. Assuming that the external clock signal is directly used in the memory device with buffering, when the external clock signal is applied to a gate of a transistor so as to enable the transistor to be active, the transistor will be maintained its active state during 5 ns. But, in practical, there are few times of retaining a transistor on an active state for 5 ns in internal operations. Thus, it would be inevitable to result in undesirable power consumption.
Further, if the external clock signal has a low frequency, an internal pulse with a narrow width, that is modified from the external clock signal, can be useful to carry out a plurality of operations in a cycle of the external clock signal.
By those reasons, the memory device needs to use an internal clock signal specifically generated to be enabled only for necessary times in active operations. In reference, it is typical for a memory device to employ a pulse generator in order to generate an internal clock signal.
Meantime, it is usual that pulse widths of a pulse signal (i.e., an internal clock signal) outputted from a pulse generator are irregular, which is denoted into “slow” signal and “fast” signal in FIG. 1A. Typically, a pulse width is minimized under a fast condition, while becomes twice of the fast condition under a slow condition. Such an irregular pulse width arises from variation of operational characteristic in a pulse generator in accordance with variations of processing conditions, pressures, temperature, and so on.
In addition, as illustrated in FIG. 1B, if a frequency of the external clock signal goes over a definite level, it becomes very difficult to properly generate an internal clock signal by mean of the pulse generator.
For instance, when the frequency of the external clock signal is about 700 MHz as shown in FIG. 1B, a cycle time of the external clock signal is about 1.4 ns and its half cycle time is 0.715 ns. Here, such a short cycle time is most unavailable to be used in generating an internal clock signal as a pulse signal by a pulse generator.
As an example, it will be considered about the case of generating an internal clock signal with a frequency of 700 MHz by means of the pulse generator.
As aforementioned, the pulse generator has an output signal variable with its pulse width due to processing parameters. Therefore, when a high level period of the pulse signal is set on 0.715 ns under the fast condition, a high level period of the pulse signal under the slow condition will be about 1.4 ns because it is two times of the fast condition. As a result, since there is no low level period of the pulse signal in fact, it is impossible for the pulse signal to function its normal operation. To the contrary, when the pulse signal is set on 0.715 ns under the slow condition, a high level period of the pulse signal will become 0.3 ns under the fast condition. However, as the pulse signal with the high level period of 0.3 ns is near a glitch signal in substance, it is also impossible for the pulse signal to be operable normally.
FIG. 2 illustrates an example of a conventional pulse generator for outputting an internal clock signal from receiving the external clock signals CLK and CLKB. Exemplary signal waveforms of FIG. 2 are shown in FIG. 1A.
In FIG. 2, the pulse generator receives an output signal from a receiver having a buffering function and outputs an internal pulse signal with a predetermined pulse width. Such a circuit for generating an internal pulse signal necessary to internal operations by employing the pulse generator is called as a pulse base device. On the other side, a circuit using an external clock signal as internal clock signal directly is referred to as a clock base device. The clock base device is used when a frequency of an external clock signal is very high, which will be described later.
FIG. 3 illustrates active periods (high level periods) of an internal clock signal when a frequency of an external clock signal is 100 MHz, 300 MHz, and 700 MHz, respectively. Slow, typ, and fast conditions illustrate characteristic differences for the devices in accordance with variations of processing parameters. Those conditions differentiate the pulse width of the internal clock signal.
In FIG. 3, when a frequency of the external clock signal is 100 MHz, a pulse generator is used to generate the internal clock signal. When a frequency of the external clock signal is 300 MHz or 700 MHz, pulse widths of pulse signals under the clock base device without the pulse generator are used.
As illustrated in FIG. 3, the conventional cases have irregular pulse widths, large differences between them as well. It is desirable to make pulse widths of an internal clock signal be uniform in order to accomplish a stable internal operation of a memory device. In other words, pulse widths of the internal clock signal used in a memory device need to be uniform, even when a frequency of external clock signal varies.
However, as illustrated in FIG. 3, the conventional case shows that pulse widths of the internal clock signal are variable in accordance with variation of a frequency of the external clock signal. Moreover, it can be seen that the differences between pulse widths are large in accordance with variations of processing parameters.
FIGS. 4A and 4B illustrate examples of conventional pulse generators.
In FIGS. 4A an 4B, an input signal IN generally corresponds to a signal passing through the receiver shown in FIG. 2, while an output signal OUT corresponds to an output signal of the pulse generator shown in FIG. 2. Accordingly, the output signal OUT corresponds to the internal clock signal.
In FIGS. 4A and 4B, a Y-time delay circuit outputs a signal applied thereto with delaying by a Y-time.
FIG. 4C is a waveform diagram when the input signal IN has a wide pulse width and FIG. 4D is a waveform diagram when the input signal IN has a short pulse width.
As can be seen from FIGS. 4C and 4D, when a frequency of an input signal applied thereto in FIGS. 4A and 4B is low (i.e., a pulse width of the input signal is wide), a designer can obtain a desired output waveform (FIG. 4C). Otherwise, when a frequency of the input signal is high (i.e., a pulse width of the input signal is narrow), it is impossible to obtain an output waveform desired by a designer.
FIG. 5A illustrates another example of a conventional pulse generator, and FIG. 5B and 5C are output waveform diagrams in accordance with a frequency of an input signal.
As illustrated, the case of FIG. 5A enables a designer to obtain a desired output waveform when a frequency of the input signal applied to the circuit of FIG. 5A is low (FIG. 5B). But, when a frequency of the input signal applied to the circuit of FIG. 5A is high, it is impossible to obtain an output waveform desired by a designer as shown in FIG. 5C.
FIG. 6A illustrates further another example of a conventional pulse generator. FIGS. 6B and 6C are output waveform diagrams in accordance with a frequency of an input signal.
As illustrated, the case of FIG. 6A enables a designer to obtain a desired output waveform when a frequency of the input signal applied to the circuit of FIG. 6A is high (FIG. 6C). But, when a frequency of the input signal applied to the circuit of FIG. 6A is low, it is impossible to obtain an output waveform desired by a designer as shown in FIG. 6B.
From considering the above, it is very difficult for the conventional cases to obtain an internal pulse signal (i.e., an internal clock signal) having a stable pulse width desired by a designer when a frequency of an input signal (i.e., an external clock signal) varies.